The present invention relates generally to a semiconductor package and a stacked semiconductor package having the same, and more particularly to a semiconductor package having chip selection through electrodes for selecting a semiconductor chip and a stacked package having the same.
Recent developments in semiconductor chip technology have lead to semiconductor chips capable of storing massive amounts of data and processing the massive amounts of data within a short time, and semiconductor packages having a plurality of the semiconductor chips.
In stacked semiconductor package technology, at least two semiconductor chips are stacked in order to enhance data storage capacity and data processing speed.
The stacked semiconductor package requires a structure adapted to select one of the stacked semiconductor chips for inputting or outputting data. In conventional stacked semiconductor packages, each semiconductor chip is formed with a different chip selection pattern making it possible to select the respective semiconductor chips.
However, this method of selecting stacked semiconductor chips requires that different pattern masks be used for the different chip selection patterns of the semiconductor chips. Having to utilize different masks to form the different chip selection patterns greatly increases the complexity of the fabrication process of the stacked semiconductor package, and increases the amount of time taken to fabricate the stacked semiconductor package.